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In verilog statements are executed concurrently, all statements in a module are executed in non-sequential order, and if statements are sequentially executed statements.

Verilog specifies that sequential execution statements must be contained in always blocks.

the ∗ sign will automatically include all signals appearing to the right of a statement or conditional expression in the always block

the output signals in the always block must be described as type reg

the if statement is a commonly used conditional statement in Verilog HDL and can be paired with the else statement or used alone.

However, if an if statement is used without an else statement, this is what happens: the compiler determines if the conditional expression following the if is satisfied, and if it is satisfied, then executes the subsequent statement, and if the conditional expression is not satisfied, the compiler automatically generates a register to hold the current value, and keeps the past value of the output when the condition is not satisfied. This creates extra registers that are not designed by the user. It is therefore recommended that the reader pair the if statement with an else statement. This prevents the creation of redundant registers.🤣